1. Field of the Invention
The present invention relates to a semiconductor apparatus (package) and a method for manufacturing the semiconductor apparatus such as CSP (Chip size package) or MCP (Multi chip package) with an integrated circuit (IC) mounted. More specifically, the present invention relates to an electric appliance installed with the package.
2. Related Art
A portable electric appliance as typified by a cellular phone or an electronic book is required various functions such as sending and receiving e-mails, speech recognition, image capturing using a small camera, and the like. On the other hand, downsizing and weight saving of the portable electric appliances needs from users are still increased. Therefore a chip having larger circuit size and larger amount of memory are necessary to be mounted on the limited capacity of the portable electric appliance.
CSP (Chip size package), which is one type of packaging, has attracted attention as a technique for mounting a chip with IC on a printed wiring board. By using CSP, the same level of downsizing and weight saving can be realized at the same level as bare chips. Different from bare chips, CSP is suitable for standardization since an electronic appliance maker is not required special machines and techniques such as a bonder or a clean room for mounting chips provided by a packaging maker. Further, CSP has advantageous functions that bare chips do not have such as a function for protecting chips from outside, a generalizing function for standardizing the footprint of a printed wiring board, and a scale conversion function for enlarging a chip with submicron scale as the millimeter scale of the printed wiring board. CSP becomes an indispensable technique to the electric appliance maker for realizing downsizing and weight saving.
For realizing further downsizing and weight saving of CSP, thinning of the chip mounted on CSP is becoming considered as a problem. For example, the following reference discloses that the target value of the chip thickness is at most 50 μm at present. (Reference 1: SEMICON Japan 2002, Dec. 5, 2002, produced by SEMI Japan, Technical programs for the semiconductor equipment and materials industries, The present state of mounting a thin chip (die), Prospects of reducing the thickness at most 50 μm, Noboru Hayasaka, Fujitsu. Co. Ltd., “Standardized examples and standardizable matters” page 1–8)
Generally, a series of process for manufacturing a chip mounted in a package as typified by CSP is provided with a process for polishing the reverse side of a silicon wafer that is referred to as back grind. By the process for polishing, a chip can be reduced its thickness, size, and weight.
However, the back grind leaves a polishing mark with approximately several ten nm in depth on the reverse side of a silicon wafer. The polishing mark causes reduction of mechanical strength of a chip. There are some cases that a crack is generated in addition to the polishing mark. The crack has a depth of several μm, in some cases, the depth extends to 20 μm. Both of the polishing mark and the crack cause chip destruction during a subsequent process. The problem becomes serious as the thickness of a chip is reduced.
For solving the problems, a process referred to as stress relief may be added after the back grind. The stress relief is carried out for flattening the reverse side of a silicon wafer, specifically, plasma etching, wet etching, dry polishing, or the like is carried out. The stress relief is effective for making the polishing mark disappear with a depth of approximately several ten nm, however it is ineffective for making cracks disappear with a depth from several to 20 μm. In addition, it becomes unfavorable that stress relief is carried out so as to make the cracks disappear since processing time becomes prolonged and the throughput in the process for manufacturing chips becomes decreased.
A device is required to be protected during back grind of the reverse side of silicon wafer by pasting a tape or a substrate over the surface of silicon wafer on which a device is formed. Thus, the total thickness, that is, the thickness of the silicon wafer, the tape, and the substrate, which are pasted for protecting the device, are controlled during the back grind. Surface irregularities approximately from several to several ten μm on the polished silicon wafer will be generated if the tape or the substrate for protecting the device has flexure or uneven thickness. Since the thickness of a silicon wafer has an effect on the characteristics of a chip that is to be manufactured, there will arise a problem of variations of the characteristics due to such uneven thickness.
In addition, the unit cost of a silicon wafer is higher than that of a glass substrate or the like. The sizes of silicon wafers that are comparatively a lot on the market are approximately not more than 12 inches in diameter. Although more than 12 inches sized silicon wafers are also on the market, the unit cost becomes further increased as increasing its size so that such silicon wafers are not suitable to provide low cost chip. However, the silicon wafer with 12 inches in diameter is not suitable for mass-production since the number of chip manufactured from one silicon wafer is limited and throughput of the silicon wafer with only 12 inches is difficult to be improved.